Semiconductor device
US7574648B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2005 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Nov 29, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When the miniaturization of a DRAM advances, the capacity of a cell capacitor decreases, and further the voltage of a data line is lowered, the amount of read signals remarkably lowers, errors are produced during readout, and the yield of chips lowers. To solve the above problems, the present invention provides a DRAM that: has an error correcting code circuit for each sub-array; detects and corrects errors with said error correcting code circuit in both the reading and writing operations; and further has rescue circuits in addition to said error correcting code circuits and replaces a defective cell caused by hard error with a redundant bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.