Method and apparatus for mitigating one or more event upsets
US7576557B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2008 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | Mar 26, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17764
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of configuring an integrated circuit having programmable logic including the steps of generating a configuration bitstream in accordance with a configuration setup, storing the configuration bitstream into a portion of a memory, configuring the programmable logic of the integrated circuit with a first configuration portion of the configuration bitstream of the memory, monitoring the integrated circuit for at least one configuration error generated in response to an event upset, reconfiguring at least a portion of the programmable logic of the integrated circuit with a second configuration portion of the configuration bitstream in response to the at least one configuration error generated. The integrated circuit may operate normally during the process of reconfiguring the at least a portion of the programmable logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.