Semiconductor device and method for manufacturing thereof
US7579677B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2006 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Mar 29, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a power semiconductor device, a joint between the power semiconductor element and frame plated with Ni is composed of a laminated structure comprising, from the power semiconductor element side, an intermetallic compound layer having a melting point of 260° C. or higher, a Cu layer, a metal layer having a melting point of 260° C. or higher, a Cu layer and an intermetallic layer having a melting point of 260° C. or higher. The structure of the joint buffers the stress generated by the secondary mounting and temperature cycle at the bond for the semiconductor element and the frame having a large difference in thermal expansion coefficient from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.