System and memory for sequential multi-plane page memory operations
US7580283B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 21, 2007 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Dec 6, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for at least one of the memory planes is initiated during the memory operation for another memory plane. In one embodiment, each of a plurality of programming circuits is associated with a respective memory plane and is operable to program data to the respective memory plane in response to programming signals and when it is enabled. Control logic coupled to the plurality of programming circuits generates programming signals in response to the memory receiving program commands and further generates programming enable signals to individually enable each of the programming circuits to respond to the programming signals and stagger programming of data to each of the memory planes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.