Power saving system and method for use with a plurality of memory circuits
US7580312B2 · kind B2 · utility
132Cited by
349References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2006 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Aug 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power saving system and method are provided. In use, at least one of a plurality of memory circuits is identified that is not currently being accessed. In response to the identification of the at least one memory circuit, a power saving operation is initiated in association with the at least one memory circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.