Interface circuit system and method for performing power saving operations during a command-related latency
US7581127B2 · kind B2 · utility
134Cited by
337References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2006 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Dec 27, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing a power management operation in association with at least a portion of the memory circuits. Such power management operation is performed during a latency associated with one or more commands directed to at least a portion of the memory circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.