Constructing a model of a programmable logic device
US7584448B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2006 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | May 12, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor-implemented method is provided for constructing a model of a programmable logic device (PLD) design. A netlist is input that describes the PLD design. An identification is input of programmable tile modules that include a programmable resource, which is either programmable interconnect or programmable logic. A first characterization data is input for sub-modules of the programmable tile modules for the programmable resource. For each programmable tile module, the routing arcs of each programmable interconnect are generated. A second characterization data is input for a configuration memory cell module of the PLD design. A third characterization data is input for a configuration control module of the PLD design. A first map is generated that links each routing arc to a bit of configuration data for programming the programmable interconnect. A second map is generated that links each logic function to a bit of configuration data for programming the programmable logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.