Packaged semiconductor die and manufacturing method thereof
US7586182B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2005 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Aug 4, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Aspects of the subject matter described herein relate to a packaged semiconductor die which becomes a component of a finished multi-chip package. The packaged semiconductor die comprises a die substrate, a semiconductor package, and a sealant. The die substrate includes an insulating substrate and a circuit pattern formed on the insulating substrate. The semiconductor package has a semiconductor chip electrically coupled to the circuit pattern that is a known good package and is coupled to the die substrate. The sealant seals the semiconductor package. The packaged semiconductor die utilizes a known good package which has passed a series of package tests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.