RF power transistor with large periphery metal-insulator-silicon shunt capacitor
US7589370B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2007 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Jan 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/66
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated MIS capacitor structure has a bottom electrode, a capacitor dielectric overlying the bottom electrode, and a plurality of capacitor top plates overlying the capacitor dielectric. In one form each capacitor top plate has a principal dimension and a lesser dimension, wherein individual capacitor top plates of the plurality are arranged proximate and adjacent to one another in an array along respective principal dimensions thereof. The bottom electrode is shared among the plurality of capacitor top plates. At least one of a plurality of conductive stripes is positioned on opposite sides of each capacitor top plate along the principal dimension of a respective capacitor top plate. The structure also has a grounded top metal layer and an inter-level dielectric. An external ground via is disposed adjacent at least one side edge of the plurality of capacitor top plates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.