System and method for power management in memory systems
US7590796B2 · kind B2 · utility
138Cited by
350References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2006 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Jun 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of physical memory circuits and a system. The interface circuit is operable to interface the physical memory circuits and the system for simulating at least one virtual memory circuit with a first power behavior that is different from a second power behavior of the physical memory circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.