Metallization layer of a semiconductor device having differently thick metal lines and a method of forming the same

US7592258B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Matthias Lehr · Dresden, DE
• Matthias Schaller · Dresden, DE
• Carsten Peters · Dresden, DE

Key dates

• Filing date: Jan 3, 2007
• Grant date: Sep 22, 2009
• Expiry date: Jun 7, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L23/5283
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device comprises metal lines in a specific metallization layer which have a different thickness and thus a different resistivity in different device regions. In this way, in high density areas of the device, metal lines of reduced thickness may be provided in order to comply with process requirements for achieving a minimum pitch between neighboring metal lines, while in other areas having less critical constraints with respect to minimum pitch, a reduced resistivity may be obtained at reduced lateral dimensions compared to conventional strategies. For this purpose, the dielectric material of the metallization layer may be appropriately patterned prior to forming respective trenches or the etch behavior of the dielectric material may be selectively adjusted in order to obtain differently deep trenches.