Inventor · Dresden, DE

Carsten Peters

36Patents
6h-index
39Co-inventors
65Inventor score

Filing activity: Jun 15, 2006 → Feb 3, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US10483154B1 Front-end-of-line device structure and method of forming such a front-end-of-line device structure Electricity 375 Active
US7902581B2 Semiconductor device comprising a contact structure based on copper and tungsten Electricity 12 Active
US10157774B1 Contact scheme for landing on different contact area levels Electricity 10 Active
US7678690B2 Semiconductor device comprising a contact structure with increased etch selectivity Electricity 9 Active
US7928004B2 Nano imprint technique with increased flexibility with respect to alignment and feature shaping Electricity 8 Active
US7416973B2 Method of increasing the etch selectivity in a contact structure of semiconductor devices Electricity 6 Active
US7764078B2 Test structure for monitoring leakage currents in a metallization layer Electricity 5 Active
US8293641B2 Nano imprint technique with increased flexibility with respect to alignment and feature shaping Electricity 4 Active
US7915170B2 Reducing contamination of semiconductor substrates during beol processing by providing a protection layer at the substrate edge Electricity 4 Active
US7592258B2 Metallization layer of a semiconductor device having differently thick metal lines and a method of forming the same Electricity 3 Active
US8173538B2 Method of selectively forming a conductive barrier layer by ALD Electricity 3 Active
US7482219B2 Technique for creating different mechanical strain by a contact etch stop layer stack with an intermediate etch stop layer Electricity 3 Active
US11213939B2 Chisel Performing Operations; Transporting 2 Active
US10252321B2 Twist drill and production method Performing Operations; Transporting 2 Active
US8932911B2 Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects Electricity 2 Active
US9257329B2 Methods for fabricating integrated circuits including densifying interlevel dielectric layers Electricity 2 Active
US7879709B2 Semiconductor structure comprising an electrically conductive feature and method of forming a semiconductor structure Electricity 2 Active
US7638424B2 Technique for non-destructive metal delamination monitoring in semiconductor devices Electricity 2 Active
US7875514B2 Technique for compensating for a difference in deposition behavior in an interlayer dielectric material Electricity 1 Active
US11031406B2 Semiconductor devices having silicon/germanium active regions with different germanium concentrations Electricity 1 Active
US7608501B2 Technique for creating different mechanical strain by forming a contact etch stop layer stack having differently modified intrinsic stress Emerging Cross-Sectional Technologies 1 Active
US11123855B2 Control method and borehole flushing module Performing Operations; Transporting 1 Active
US9305878B2 Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects Electricity 1 Active
US7998823B2 Method for reducing leakage currents caused by misalignment of a contact structure by increasing an error tolerance of the contact patterning process Electricity 0 Active
US10906166B2 Control method and portable power tool Performing Operations; Transporting 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.