Method for manufacturing MOS transistors utilizing a hybrid hard mask
US7592262B2 · kind B2 · utility
6Cited by
3References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2007 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Dec 29, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing MOS transistor with hybrid hard mask includes providing a substrate having a dielectric layer and a polysilicon layer thereon, forming a hybrid hard mask having a middle hard mask and a spacer hard mask covering sidewalls of the middle hard mask on the polysilicon layer, performing a first etching process to etch the polysilicon layer and the dielectric layer through the hybrid hard mask to form a gate structure, performing a second etching process to form recesses in the substrate at two sides of the gate structure, and performing a SEG process to form epitaxial silicon layers in each recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.