Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy
US7594967B2 · kind B2 · utility
3Cited by
158References
46Claims
0Family size
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Key dates
| Filing date | Oct 10, 2002 |
| Grant date | Sep 29, 2009 |
| Priority date | — |
| Expiry date | Sep 20, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S117/913
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure including a cap layer formed over a semiconductor substrate having a rough edge, which discourages formation of dislocation pile-up defects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.