Method for manufacturing strip level substrate without warpage and method for manufacturing semiconductor package using the same
US7595255B2 · kind B2 · utility
2Cited by
2References
10Claims
0Family size
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Key dates
| Filing date | Jun 8, 2007 |
| Grant date | Sep 29, 2009 |
| Priority date | — |
| Expiry date | Oct 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/0989
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A strip level substrate is manufactured by: applying solder resist on a substrate including a plurality of unit substrate divided by a scribe line; and patterning the applied solder resist to expose an electrode terminal and a ball land in each unit substrate, wherein the patterning of the solder resist is performed to be removed together with a solder resist part applied on the scribe line in order to reduce an early warpage of the strip level substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.