Method of manufacturing semiconductor integrated circuit device having capacitor element
US7598558B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2007 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Dec 19, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.