NOR flash memory
US7598561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2006 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Jun 3, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor memory array and process of fabrication in which a plurality of bit line diffusions are formed in a substrate, and memory cells formed in pairs between the bit line diffusions, with each of the pairs of cells having first and second conductors adjacent to the bit line diffusions, floating gates beside the first and second conductors, an erase gate between the floating gates, and a source line diffusion in the substrate beneath the erase gate, and at least one additional conductor capacitively coupled to the floating gates. In some disclosed embodiments, the conductors adjacent to the bit line diffusions are word lines, and the additional conductors consist of either a pair of coupling gates which are coupled to respective ones of the floating gates or a single coupling gate which is coupled to both of the floating gates. In another embodiment, the conductors adjacent to the bit line diffusions are program lines, and the third conductors are word lines which extend in a direction perpendicular to the program lines and the diffusions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.