Binary polynomial multiplier
US7599981B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2001 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | May 24, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/724
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiply unit includes support for arithmetic operations, binary polynomial operations, and permutations. To this end, the multiply unit may include an input data path that receives input operands, an arithmetic multiplier connected to receive the input operands, a binary polynomial multiplier having components separate and distinct from the arithmetic multiplier and connected to receive the one or more input operands, and a multiply unit output data path connected to receive an output of the arithmetic multiplier and connected to receive an output of the binary polynomial multiplier. The multiply unit also may include permutation logic that performs permutation operations on the input operands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.