Stress-managed revision of integrated circuit layouts
US7600207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2006 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Jul 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.