Methods for fabricating a stress enhanced MOS transistor
US7601574B2 · kind B2 · utility
12Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Oct 25, 2006 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Jan 11, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/021
Abstract
Methods are provided for fabricating a stress enhanced MOS transistor. One such method comprises the steps of depositing and patterning a layer of sacrificial material to form a dummy gate electrode and replacing the dummy gate electrode with a stressed gate electrode. After the stressed gate electrode has been formed by a replacement process, a stress liner is deposited overlying the stressed gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.