Two step optical planarizing layer etch
US7601641B1 · kind B1 · utility
8Cited by
0References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2008 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Mar 31, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0271
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods are provided for etching during fabrication of a semiconductor device. The method includes initially etching to partially remove a portion of one or more lithographic-aiding layers overlying an oxide layer while etching a first portion of the oxide layer in accordance with a mask formed by the one or more lithographic-aiding layers, and thereafter additionally etching to remove remaining portions of the one or more lithographic-aiding layers while etching a remaining portion of the oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.