Top-oxide-early process and array top oxide planarization
US7601646B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2004 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Feb 3, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.