Semiconductor device having a sense amplifier array with adjacent ECC
US7603592B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 31, 2006 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Jul 31, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such as DRAM, and an error correction code circuit required therein is disposed near a sense amplifier array. In addition to normal memory arrays composed of such memory arrays, a redundant memory array having a sense amplifier array and an error correction code circuit adjacent thereto is provided in a chip. By this means, the error which occurs in the manufacture can be replaced. Also, the error correction code circuit corrects the error at the time of an activate command and stores the check bit at the time of a pre-charge command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.