Stacked integrated circuit assembly
US7605477B2 · kind B2 · utility
5Cited by
12References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2007 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Aug 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked integrated circuit assembly includes a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC is disposed between the substrate and the SFIC. The stacked integrated circuit assembly includes least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.