Erase verifying method of NAND flash memory device
US7606080B2 · kind B2 · utility
7Cited by
5References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2007 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Apr 7, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/344
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an erase verifying method of a NAND flash memory device, a power supply voltage (Vcc) is applied to a second bit line while precharging a first bit line to a first positive voltage. Select transistors are turned on, and a ground voltage is applied to word lines of memory cell transistors. A second positive voltage is applied to source lines to which sources of the select transistors and the memory cell transistors are connected. An erased state of the memory cell transistor is verified according to whether charges accumulated in the first bit line are discharged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.