Shrink test mode to identify Nth order speed paths
US7607061B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2007 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Apr 8, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31727
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In one embodiment, an integrated circuit comprises first circuitry; a first clock generator coupled to supply a first clock to the first circuitry, and a control unit coupled to the first clock generator. The first clock generator is coupled to receive an input clock to the integrated circuit and is configured to generate the first clock. The control unit is also coupled to receive a trigger input to the integrated circuit. During a test of the integrated circuit, the control unit is configured to cause the first clock generator to generate the first clock at a first clock frequency, The control unit is configured to cause the first clock generator to generate the first clock at a second frequency greater than the first clock frequency for at least one clock cycle responsive to an assertion of the trigger input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.