Alignment of trench for MOS

US7608510B2 · kind B2 · utility

Assignee

• AMI Semiconductor Belgium BVBA · BE

Inventors

• Peter Moens · Zottegem, BE
• Marnix Tack · Merelbeke, BE

Key dates

• Filing date: Apr 24, 2006
• Grant date: Oct 27, 2009
• Expiry date: Feb 24, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/252

Abstract

Manufacturing a power transistor by forming a gate structure on a first layer, forming a trench in the first layer, self aligned with the gate structure, and forming part of the transistor in the trench. By forming a spacer next to the gate, the spacer and gate can be used as a mask when forming the trench, to allow space for a source region next to the gate. The self-aligning rather than forming the gate after the trench means the alignment is more accurate, allowing size reduction. Another aspect involves forming a trench in a first layer, filling the trench, forming a second layer on either side of the trench with lateral overgrowth over the trench, and forming a source region in the second layer to overlap the trench. This overlap can enable the chip area to be reduced.