Multi-channel transistor structure and method of making thereof
US7608893B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 26, 2008 |
| Grant date | Oct 27, 2009 |
| Priority date | — |
| Expiry date | Apr 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method of forming an electronic device includes, forming a first channel coupled to a first current electrode and a second current electrode and forming a second channel coupled to the first current electrode and the second current electrode. The method also includes the second channel being substantially parallel to the first channel within a first plane, wherein the first plane is parallel to a major surface of a substrate over which the first channel lies. A gate electrode is formed surrounding the first channel and the second channel in a second plane, wherein the second plane is perpendicular to the major surface of the substrate. The resulting semiconductor device has a plurality of locations with a plurality of channels at each location. At small dimensions the channels form quantum wires connecting the source and drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.