Logic process DRAM
US7609538B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2006 |
| Grant date | Oct 27, 2009 |
| Priority date | — |
| Expiry date | Jan 16, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device includes a dynamic random access memory (DRAM) unit. The DRAM unit comprises a plurality of bit line pairs. Each bit line pair includes a first bit line and a second bit line. The first bit line and the second bit line within each bit line pair are aligned adjacent to each other. Each of a plurality of word lines is associated with the bit lines such that an array is formed by the bit lines and the associated word lines. Each bit line is associated with both first and second interconnect layers. Each of a plurality of memory cells is associated with every other bit line along each word line. Each of a plurality of amplifiers is in communication with a first bit line and a second bit line within a bit line pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.