Memory cells with lower power consumption during a write operation
US7609541B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2006 |
| Grant date | Oct 27, 2009 |
| Priority date | — |
| Expiry date | Mar 12, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell including an access transistor coupled to a first storage node and a read port coupled to one of the first storage node or a second storage node is provided. The memory cell further includes a first inverter having an input terminal coupled to the first storage node, an output terminal, and a first power supply voltage terminal for receiving a first power supply voltage. The memory cell further includes a second inverter having an input terminal coupled to the output terminal of the first inverter, an output terminal coupled to the input terminal of the first inverter at the first storage node, and a second power supply voltage terminal for receiving a second power supply voltage, wherein the second power supply voltage is varied relative to the first power supply voltage during a write operation to the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.