Patent · US Active

Apparatus and method for saving power in a trace cache

US7610449B2 · kind B2 · utility

1Cited by

38References

12Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Gordon Taylor Davis · Boca Raton, US
Richard W. Doing · Raleigh, US
John D. Jabusch · Endwell, US
M V V Anil Krishna · Cary, US
Brett Olsson · Cary, US
Eric F. Robinson · Raleigh, US
Sumedh W. Sathaye · Austin, US
Jeffrey R. Summers · Raleigh, US

Key dates

Filing date	Oct 4, 2006
Grant date	Oct 27, 2009
Priority date	—
Expiry date	Sep 5, 2027

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Power is conserved by guiding access to lines stored in the cache and lowering cache clock speed relative to the central processor clock speed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.