Modifying a test pattern to control power supply noise
US7610531B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2006 |
| Grant date | Oct 27, 2009 |
| Priority date | — |
| Expiry date | Oct 20, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318575
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Mechanisms for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a circuit voltage, e.g., an on-chip voltage, which approximates a nominal circuit voltage, such as produced by the application of other portions of the sequence of states in the same or different test sequences. For example, hold state cycles or shift-scan state cycles may be inserted or removed prior to test state cycles in the test pattern waveform. The insertion/removal shifts the occurrence of the test state cycles within the test pattern waveform so as to adjust the voltage response of the test state cycles so that they more closely approximate a nominal voltage response. In this way, false failures due to noise in the voltage supply may be eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.