Method of minimizing kerf width on a semiconductor substrate panel
US7611927B2 · kind B2 · utility
2Cited by
4References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2007 |
| Grant date | Nov 3, 2009 |
| Priority date | — |
| Expiry date | Sep 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/175
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.