Decoding system capable of reducing sector select area overhead for flash memory
US7613042B2 · kind B2 · utility
3Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2007 |
| Grant date | Nov 3, 2009 |
| Priority date | — |
| Expiry date | Jan 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/691
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are disclosed for erasing memory cells in a virtual ground memory core, wherein a row decoder apparatus employs a protective voltage to wordlines of a sector of cells while concurrently providing an erase voltage to selected wordlines of the same physical sector. Decoder circuitry and methods are disclosed for selecting a memory cell sector to be erased and adjacent sectors to be protected, which may be used in single bit and dual bit memory devices, and which enable column decoder circuitry to reduce the number of sector select circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.