Methods, circuits, and systems to select memory regions
US7613060B2 · kind B2 · utility
9Cited by
10References
13Claims
0Family size
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Key dates
| Filing date | May 21, 2007 |
| Grant date | Nov 3, 2009 |
| Priority date | — |
| Expiry date | Jun 15, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments for selecting regions of memory are described. For example, in one embodiment a memory device having an array of memory cells includes an array selection block. The array selection block receives an input signal indicative of a region in the array of memory cells. The array selection block generates a selection signal to map the region to at least one physical location in the array of memory cells, based on the detection of the number of defects in that location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.