Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler
US7613904B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2005 |
| Grant date | Nov 3, 2009 |
| Priority date | — |
| Expiry date | Aug 22, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bifurcated instruction scheduler for dispatching instructions of multiple threads concurrently executing in a multithreading processor is provided. The scheduler includes a first portion within a reusable core that is not customizable by a customer, a second portion outside the core that is customizable, and an interface coupling the second portion to the core. The second portion implements a thread scheduling policy that may be customized to the customer's particular application. The first portion may be scheduling policy-agnostic and issues instructions of the threads each clock cycle to execution units based on the scheduling policy communicated by the second portion. The second portion communicates the scheduling policy via a priority for each of the threads. When the core commits an instruction for execution, the core communicates to the second portion which thread the committed instruction is in to enable the second portion to update the priorities in response thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.