Elevated source and drain elements for strained-channel heterojuntion field-effect transistors
US7615829B2 · kind B2 · utility
7Cited by
215References
1Claims
0Family size
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Key dates
| Filing date | Jun 7, 2002 |
| Grant date | Nov 10, 2009 |
| Priority date | — |
| Expiry date | Aug 13, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/801
Abstract
A semiconductor structure having a surface layer disposed over a substrate, the surface layer including strained silicon. A contact layer is disposed over a portion of the surface layer, the contact layer including a metal-semiconductor alloy. A bottommost boundary of the contact layer is disposed above a bottommost boundary of the surface layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.