Wafer edge inspection and metrology
US7616804B2 · kind B2 · utility
13Cited by
4References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2006 |
| Grant date | Nov 10, 2009 |
| Priority date | — |
| Expiry date | Apr 23, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N21/9503
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Some aspects of the present invention relate to a wafer inspection method. A plurality of images is acquired about an edge portion of a wafer. Each of the images comprises a pixel array having a first dimension and a second dimension. A composite image of compressed pixel arrays is generated by compressing each of the pixel arrays in the first dimension and concatenating the pixel arrays. The composite image is analyzed to identify a wafer feature, for example using a sinusoidal line fit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.