Semiconductor package-on-package (POP) device avoiding crack at solder joints of micro contacts during package stacking
US7619305B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2007 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | Feb 26, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked semiconductor device primarily comprises semiconductor packages with a plurality of micro contacts and solder paste to soldering the micro contacts. Each semiconductor package comprises a substrate and a chip disposed on the substrate. The micro contacts of the bottom semiconductor package are a plurality of top bumps located on the upper surface of the substrate. The micro contacts of the top semiconductor package are a plurality of bottom bumps located on the lower surface of the substrate. The bottom bumps are aligned with the top bumps and are electrically connected each other by the solder paste. Therefore, the top bumps and the bottom bumps have the same soldering shapes and dimensions for evenly soldering to avoid breakages of the micro bumps during stacking.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.