Sige channel epitaxial development for high-k PFET manufacturability

US7622341B2 · kind B2 · utility

Assignees

• International Business Machines Corporation · US
• Advanced Micro Devices, Inc. · US

Inventors

• Michael P. Chudzik · Beacon, US
• Dominic J. Schepis · Wappingers Falls, US
• Linda Black · Wappingers Falls, US

Key dates

• Filing date: Jan 16, 2008
• Grant date: Nov 24, 2009
• Expiry date: May 7, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76229
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for growing an epitaxial layer patterns a mask over a substrate. The mask protects first areas (N-type areas) of the substrate where N-type field effect transistors (NFETs) are to be formed and exposes second areas (P-type areas) of the substrate where P-type field effect transistors (PFETs) are to be formed. Using the mask, the method can then epitaxially grow the Silicon Germanium layer only on the P-type areas. The mask is then removed and shallow trench isolation (STI) trenches are patterned (using a different mask) in the N-type areas and in the P-type areas. This STI patterning process positions the STI trenches so as to remove edges of the epitaxial layer. The trenches are then filled with an isolation material. Finally, the NFETs are formed to have first metal gates and the PFETs are formed to have second metal gates that are different than the first metal gates. The first metal gates have a different work function than the second metal gates.