Multi-step gate structure and method for preparing the same
US7622352B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 25, 2006 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Aug 8, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-step gate structure comprises a semiconductor substrate having a multi-step structure, a gate oxide layer positioned on the multi-step structure and a conductive layer positioned on the gate oxide layer. Preferably, the gate oxide layer has different thicknesses on each step surface of the multi-step structure. In addition, the multi-step gate structure further comprises a plurality of doped regions positioned in the semiconductor substrate under the multi-step structure. The channel length of the multi-step gate structure is the summation of the lateral width and the vertical depth of the multi-step gate structure, which is dramatically increased such that problems originated from the short channel effect can be effectively solved. Further, the plurality of doped regions under the multi-step structure are prepared by implanting processes having different dosages and dopants, which can control the thickness of the gate oxide layer and the threshold voltage of the multi-step gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.