Bond pad for wafer and package for CMOS imager
US7622364B2 · kind B2 · utility
38Cited by
3References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2006 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Oct 13, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.