Gate electrode silicidation process
US7622387B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Aug 29, 2005 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Aug 29, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fully-silicided gate electrode is formed from silicon and a metal by depositing at least two layers of silicon with the metal layer therebetween. One of the silicon layers may be amorphous silicon whereas the other silicon layer may be polycrystalline silicon. The silicon between the metal layer and the gate dielectric may be deposited in two layers having different crystallinities. This process enables greater control to be exercised over the phase of the silicide resulting from this silicidation process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.