Semiconductor device having shallow trench isolation structure comprising an upper trench and a lower trench including a void
US7622778B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2006 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Nov 24, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76232
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a semiconductor device has an active region defined by an isolation layer formed inside an STI trench that includes an upper trench and a lower trench having a substantially curved cross-sectional profile under the upper trench so that the lower trench is in communication with the upper trench. Since the upper trench has a sidewall tapered with a positive slope, a good gap filling property can be obtained when filling the upper trench with an insulating layer. By forming a void in the lower trench, a dielectric constant at the bottom of the isolation layer is lower than a dielectric constant at an oxide layer, thereby improving the isolation property. The isolation layer includes a first insulating layer formed inside only the upper trench and covering an inner wall of the upper trench in the form of a spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.