High performance input receiver circuit for reduced-swing inputs
US7622986B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2005 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Oct 2, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An input buffer receiver circuit for electronic devices (e.g., memory chips) to receive and process reduced-swing and high bandwidth inputs to obtain “buffered” output signals therefrom with symmetrical rising and falling delays, and without additional current dissipation over previous receiver circuits, is disclosed. The receiver circuit may include two stages of differential amplifier pairs (i.e., a total of 4 separated differential amplifiers). The differential amplifiers in the first stage convert the single-ended input signal to a full-differential signal, which is then converted back to a single-ended output signal by the differential amplifier pair in the second stage. The output of a P-diff first stage may be connected to the input of an N-diff second stage and the output of an N-diff first stage may be connected to the input of a P-diff second stage thereby creating a “cross” coupled structure. Various current saving and biasing methods may also be employed to keep the operating current the same or lower than the previous receiver circuit designs. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.