Method of reading flash memory device for depressing read disturb
US7623385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2007 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Mar 16, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a method of reading a flash memory device for depressing read disturb. According to the method, a first voltage is applied to a gate of the drain select transistor to turn on the drain select transistor, and a read voltage is applied to a gate of a selected transistor among the plurality of memory cells. Then, a pass voltage is applied to gates of unselected transistors among the plurality of memory cells. Furthermore, when the pass voltage is applied, a first pass voltage is applied and then a second pass voltage is applied after an elapse of a predetermined time following the applying of the first pass voltage. The second pass voltage has a level different from that of the first pass voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.