Methods of making spintronic devices with constrained spintronic dopant
US7625767B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2007 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Feb 4, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01F10/3268
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method is for making a spintronic device and may include forming at least one superlattice and at least one electrical contact coupled thereto, with the at least one superlattice including a plurality of groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and a spintronic dopant. The spintronic dopant may be constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer. In some embodiments, the repeating structure of a superlattice may not be needed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.