Method for forming vias in a substrate
US7625818B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 31, 2008 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Jul 31, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76898
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method for forming vias in a substrate, comprising the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a photo resist layer on the first surface of the substrate; (c) forming a pattern on the photo resist layer; (d) forming a groove and a pillar in the substrate according to the pattern, wherein the groove surrounds the pillar; (e) forming a polymer in the groove of the substrate; (f) removing the pillar of the substrate to form an accommodating space; (g) forming a conductive metal in the accommodating space; and (h) removing part of the second surface of the substrate to expose the conductive metal and the polymer. As a result, thicker polymer can be formed in the groove, and the thickness of the polymer in the groove is uniform.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.