Interconnection process
US7625819B2 · kind B2 · utility
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1References
10Claims
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Assignee
Inventors
Key dates
| Filing date | Jun 1, 2007 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Jul 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76828
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnection process is provided. The process includes the following steps. Firstly, a semiconductor base having at least a electrical conductive region is provided. Next, a dielectric layer with a contact hole is formed to cover the semiconductor base, wherein the contact hole exposes part of the electrical conductive region. Then, a thermal process is performed on the semiconductor base covered with the dielectric layer. Lastly, a conductive layer is formed on the dielectric layer, wherein the conductive layer is electrically connected to the electrical conductive region through the contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.