Semiconductor devices and methods of manufacture thereof
US7626257B2 · kind B2 · utility
19Cited by
13References
45Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 18, 2006 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Mar 29, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Vertically stacked integrated circuits and methods of fabrication thereof are disclosed. Deep vias that provide vertical electrical connection for vertically stacked integrated circuits are formed early in the manufacturing process, before integrated circuits are bonded together to form a three dimensional integrated circuit (3D-IC).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.